Vlsi Implementation of Mimo Signal Processing Algorithms

Vlsi Implementation of Mimo Signal Processing Algorithms
Author: Mahdi Shabany
Publisher: LAP Lambert Academic Publishing
Total Pages: 208
Release: 2012-05
Genre:
ISBN: 9783848497638
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The efficient high-throughput VLSI implementation of near-optimal multiple-input multiple-output (MIMO) detectors for MIMO systems with large number of antennas in high-order quadrature amplitude modulation (QAM) schemes has been a major challenge in the literature. To address this challenge, this book introduces a novel scalable pipelined VLSI ar- chitecture for a 4 X 4 64-QAM MIMO receiver based on K-Best lattice decoders. The key contribution is a means of expanding/visiting the intermediate nodes of the search tree on-demand, rather than exhaustively along with three types of dis- tributed sorters operating in a pipelined structure. The combined expansion and sorting cores are able to find the K best candidates in K clock cycles. The pro- posed architecture has a fixed critical path independent of the constellation order, on-demand expansion scheme, efficient distributed sorters, and is scalable to a higher number of antennas/constellation orders. Fabricated in 0.13um CMOS, it operates at a significantly higher throughput than currently reported schemes.

VLSI Implementation of Digital Signal Processing Algorithms for MIMO/SISO Systems

VLSI Implementation of Digital Signal Processing Algorithms for MIMO/SISO Systems
Author: Mahdi Shabany
Publisher:
Total Pages: 400
Release: 2009
Genre:
ISBN: 9780494713693
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The efficient high-throughput VLSI implementation of near-optimal multiple-input multiple-output (MIMO) detectors for 4x4 MIMO systems in high-order quadrature amplitude modulation (QAM) schemes has been a major challenge in the literature. To address this challenge, this thesis introduces a novel scalable pipelined VLSI architecture for a 4 x 4 64-QAM MIMO receiver based on K-Best lattice decoders. The key contribution is a means of expanding/visiting the intermediate nodes of the search tree on-demand, rather than exhaustively along with three types of distributed sorters operating in a pipelined structure. The combined expansion and sorting cores are able to find the K best candidates in K clock cycles. The proposed architecture has a fixed critical path independent of the constellation order, on-demand expansion scheme, efficient distributed sorters, and is scalable to a higher number of antennas/constellation orders. Fabricated in 0.13mum CMOS, it operates at a significantly higher throughput (5.8x better) than currently reported schemes and occupies 0.95 mm2 core area. Operating at 282 MHz clock frequency, it dissipates 135 mW at 1.3 V supply with no performance loss. It achieves an SNR-independent decoding throughput of 675 Mbps satisfying the requirements of IEEE 802.16m and Long Term Evolution (LTE) systems. The measurements confirm that this design consumes 3.0x less energy/bit compared to the previous best design.

VLSI Implementation of Digital Signal Processing Algorithms for MIMO/SISO Systems

VLSI Implementation of Digital Signal Processing Algorithms for MIMO/SISO Systems
Author:
Publisher:
Total Pages:
Release: 2003
Genre:
ISBN:
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The efficient high-throughput VLSI implementation of near-optimal multiple-input multiple-output (MIMO) detectors for 4x4 MIMO systems in high-order quadrature amplitude modulation (QAM) schemes has been a major challenge in the literature. To address this challenge, this thesis introduces a novel scalable pipelined VLSI architecture for a 4x4 64-QAM MIMO receiver based on K-Best lattice decoders. The key contribution is a means of expanding/visiting the intermediate nodes of the search tree on-demand, rather than exhaustively along with three types of distributed sorters operating in a pipelined structure. The combined expansion and sorting cores are able to find the K best candidates in K clock cycles. The proposed architecture has a fixed critical path independent of the constellation order, on-demand expansion scheme, efficient distributed sorters, and is scalable to a higher number of antennas/constellation orders. Fabricated in 0.13um CMOS, it operates at a significantly higher throughput (5.8x better) than currently reported schemes and occupies 0.95 mm2 core area. Operating at 282 MHz clock frequency, it dissipates 135 mW at 1.3 V supply with no performance loss. It achieves an SNR-independent decoding throughput of 675 Mbps satisfying the requirements of IEEE 802.16m and Long Term Evolution (LTE) systems. The measurements confirm that this design consumes 3.0x less energy/bit compared to the previous best design.

Algorithms and VLSI Implementations of MIMO Detection

Algorithms and VLSI Implementations of MIMO Detection
Author: Ibrahim A. Bello
Publisher: Springer Nature
Total Pages: 162
Release: 2022-07-22
Genre: Technology & Engineering
ISBN: 3031045122
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This book provides a detailed overview of detection algorithms for multiple-input multiple-output (MIMO) communications systems focusing on their hardware realisation. The book begins by analysing the maximum likelihood detector, which provides the optimal bit error rate performance in an uncoded communications system. However, the maximum likelihood detector experiences a high complexity that scales exponentially with the number of antennas, which makes it impractical for real-time communications systems. The authors proceed to discuss lower-complexity detection algorithms such as zero-forcing, sphere decoding, and the K-best algorithm, with the aid of detailed algorithmic analysis and several MATLAB code examples. Furthermore, different design examples of MIMO detection algorithms and their hardware implementation results are presented and discussed. Finally, an ASIC design flow for implementing MIMO detection algorithms in hardware is provided, including the system simulation and modelling steps and register transfer level modelling using hardware description languages. Provides an overview of MIMO detection algorithms and discusses their corresponding hardware implementations in detail; Highlights architectural considerations of MIMO detectors in achieving low power consumption and high throughput; Discusses design tradeoffs that will guide readers’ efforts when implementing MIMO algorithms in hardware; Describes a broad range of implementations of different MIMO detectors, enabling readers to make informed design decisions based on their application requirements.

Massive MIMO Detection Algorithm and VLSI Architecture

Massive MIMO Detection Algorithm and VLSI Architecture
Author: Leibo Liu
Publisher: Springer
Total Pages: 348
Release: 2019-02-20
Genre: Computers
ISBN: 9811363625
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This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error. After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method.

Space-Time Processing for MIMO Communications

Space-Time Processing for MIMO Communications
Author: Alex Gershman
Publisher: John Wiley & Sons
Total Pages: 388
Release: 2005-08-05
Genre: Technology & Engineering
ISBN: 0470010037
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Driven by the desire to boost the quality of service of wireless systems closer to that afforded by wireline systems, space-time processing for multiple-input multiple-output (MIMO) wireless communications research has drawn remarkable interest in recent years. Exciting theoretical advances have been complemented by rapid transition of research results to industry products and services, thus creating a vibrant new area. Space-time processing is a broad area, owing in part to the underlying convergence of information theory, communications and signal processing research that brought it to fruition. This book presents a balanced and timely introduction to space-time processing for MIMO communications, including highlights of emerging trends, such as spatial multiplexing and joint transceiver optimization. Includes detailed coverage of wireless channel sounding, modelling, characterization and model validation. Provides state-of-the-art research results on space-time coding, including comprehensive tutorial coverage of orthogonal space-time block codes. Discusses important recent developments in spatial multiplexing, transmit beam-forming, pre-coding and joint transceiver design for the multi-user MIMO downlink using full or partial CSI. Illustrates all theory with numerous examples gleaned from cutting-edge research from around the globe. This valuable resource will appeal to engineers, developers and consultants involved in the design and implementation of space-time processing for MIMO communications. Its accessible format, amply illustrated with real world case studies, contains relevant, detailed advice for postgraduate students and researchers specializing in this field.

Baseband Receiver Design for Wireless MIMO-OFDM Communications

Baseband Receiver Design for Wireless MIMO-OFDM Communications
Author: Tzi-Dar Chiueh
Publisher: John Wiley & Sons
Total Pages: 388
Release: 2012-04-24
Genre: Technology & Engineering
ISBN: 1118188217
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The Second Edition of OFDM Baseband Receiver Design for Wirless Communications, this book expands on the earlier edition with enhanced coverage of MIMO techniques, additional baseband algorithms, and more IC design examples. The authors cover the full range of OFDM technology, from theories and algorithms to architectures and circuits. The book gives a concise yet comprehensive look at digital communication fundamentals before explaining signal processing algorithms in receivers. The authors give detailed treatment of hardware issues - from architecture to IC implementation. Links OFDM and MIMO theory with hardware implementation Enables the reader to transfer communication received concepts into hardware; design wireless receivers with acceptable implemntation loss; achieve low-power designs Covers the latest standards, such as DVB-T2, WiMax, LTE and LTE-A Includes more baseband algorithms, like soft-decoding algorithms such as BCJR and SOVA Expanded treatment of channel models, detection algorithms and MIMO techniques Features concrete design examples of WiMAX systems and cognitive radio apllications Companion website with lecture slides for instructors Based on materials developed for a course in digital communication IC design, this book is ideal for graduate students and researchers in VLSI design, wireless communications, and communications signal processing. Practicing engineers working on algorithms or hardware for wireless communications devices will also find this to be a key reference.

K-Best Decoders for 5G+ Wireless Communication

K-Best Decoders for 5G+ Wireless Communication
Author: Mehnaz Rahman
Publisher: Springer
Total Pages: 75
Release: 2016-08-31
Genre: Technology & Engineering
ISBN: 3319428098
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This book discusses new, efficient and hardware realizable algorithms that can attain the performance of beyond 5G wireless communication. The authors explain topics gradually, stepping from basic MIMO detection to optimized schemes for both hard and soft domain MIMO detection and also to the feasible VLSI implementation, scalable to any MIMO configuration (including massive MIMO, used in satellite/space communication). The techniques described in this book enable readers to implement real designs, with reduced computational complexity and improved performance.