Abstract: "We discuss the problem of accurate analysis and tuning of pre-hardware processor performance. In particular, we focus our attention to a class of current high-end super scalar, RISC processors. We examine the spectrum of performance estimation and analysis tools from those used in early-stage design point definition to later-stage cycle- accurate simulation models. The problem of 'performance verification' is highlighted as one which is becoming increasingly important, as single- chip processor complexity increases to the point where 'designer intuition' alone is not enough to ensure elimination of major 'performance bugs.' We discuss currently used methods to validate performance estimates against expectations derived from the basic hardware and application constraints. Through judicious choice of methods or tools and corresponding validation aids, the designer is able to safeguard against introduction of performance inhibitors which may be hard to remedy after 'first silicon.' Also, using such analysis and verification techniques, the designer is able to prevent post-hardware surprises with respect to benchmark performance targets (e.g. SPECmarks). We illustrate our methodology in the context of realistic examples taken from the high-end PowerPC[superscript TM] processor arena."