Heterogeneous SoC Design and Verification
Author | : Khaled Salah Mohamed |
Publisher | : Springer Nature |
Total Pages | : 177 |
Release | : |
Genre | : |
ISBN | : 303156152X |
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Author | : Khaled Salah Mohamed |
Publisher | : Springer Nature |
Total Pages | : 177 |
Release | : |
Genre | : |
ISBN | : 303156152X |
Author | : Ashok B. Mehta |
Publisher | : Springer |
Total Pages | : 346 |
Release | : 2017-06-28 |
Genre | : Technology & Engineering |
ISBN | : 3319594184 |
This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.
Author | : Muhammad Hassan |
Publisher | : Springer Nature |
Total Pages | : 181 |
Release | : 2022-09-01 |
Genre | : Technology & Engineering |
ISBN | : 3031055748 |
This book describes a comprehensive combination of methodologies that strongly enhance the modern Virtual Prototype (VP)-based verification flow for heterogeneous systems-on-chip (SOCs). In particular, the book combines verification and analysis aspects across various stages of the VP-based verification flow, providing a new perspective on verification by leveraging advanced techniques, like metamorphic testing, data flow testing, and information flow testing. In addition, the book puts a strong emphasis on advanced coverage-driven methodologies to verify the functional behavior of the SOC as well as ensure its security. Provides an extensive introduction to the modern VP-based verification flow for heterogeneous SOCs; Introduces a novel metamorphic testing technique for heterogeneous SOCs which does not require reference models; Includes automated advanced data flow coverage-driven methodologies tailored for SystemC/AMS-based VPs; Describes enhanced functional coverage-driven methodologies to verify various functional behaviors of RF amplifiers.
Author | : Sudipta Kundu |
Publisher | : Springer Science & Business Media |
Total Pages | : 176 |
Release | : 2011-05-18 |
Genre | : Technology & Engineering |
ISBN | : 1441993592 |
Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design. While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of system-level designs, the focus so far for validation purposes has been on traditional testing techniques such as random testing and scenario-based testing. This book focuses on high-level verification, presenting a design methodology that relies upon advances in synthesis techniques as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically. The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL.
Author | : Sorin Alexander Huss |
Publisher | : Springer Science & Business Media |
Total Pages | : 352 |
Release | : 2007-07-19 |
Genre | : Technology & Engineering |
ISBN | : 1402061498 |
This book is the latest contribution to the Chip Design Languages series and it consists of selected papers presented at the Forum on Specifications and Design Languages (FDL'06), in September 2006. The book represents the state-of-the-art in research and practice, and it identifies new research directions. It highlights the role of specification and modelling languages, and presents practical experiences with specification and modelling languages.
Author | : Luciano Lavagno |
Publisher | : CRC Press |
Total Pages | : 644 |
Release | : 2017-12-19 |
Genre | : Technology & Engineering |
ISBN | : 1482254638 |
The first of two volumes in the Electronic Design Automation for Integrated Circuits Handbook, Second Edition, Electronic Design Automation for IC System Design, Verification, and Testing thoroughly examines system-level design, microarchitectural design, logic verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for integrated circuit (IC) designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more. New to This Edition: Major updates appearing in the initial phases of the design flow, where the level of abstraction keeps rising to support more functionality with lower non-recurring engineering (NRE) costs Significant revisions reflected in the final phases of the design flow, where the complexity due to smaller and smaller geometries is compounded by the slow progress of shorter wavelength lithography New coverage of cutting-edge applications and approaches realized in the decade since publication of the previous edition—these are illustrated by new chapters on high-level synthesis, system-on-chip (SoC) block-based design, and back-annotating system-level models Offering improved depth and modernity, Electronic Design Automation for IC System Design, Verification, and Testing provides a valuable, state-of-the-art reference for electronic design automation (EDA) students, researchers, and professionals.
Author | : Hongce Zhang |
Publisher | : |
Total Pages | : 0 |
Release | : 2021 |
Genre | : |
ISBN | : |
Modern computing platforms are getting increasingly heterogeneous with domain-specific hardware accelerators. The heterogeneity provides efficiency in computation, however, it also brings about new challenges in specification and verification.Previously, for general-purpose processors, the instruction set architecture (ISA) created a separation between the hardware and software in terms of design and verification. It decoupled the development of a software program from the hardware implementation of the processor. Verification of hardware and software could be conducted separately with ISA as a specification for the hardware, or an abstraction of the hardware for the software. However, for specialized hardware accelerators in emerging systems-on-chip (SoCs), there is no such ISA-like model for the interface. Existing abstract models built in languages like SystemC do not specifically target the hardware-software interface, and therefore, are hard to use to separate the design and verification concerns between hardware and software.This thesis considers the instruction-level abstraction (ILA) as a generalization of the ISA to include domain-specific accelerators in heterogeneous SoCs. It first provides a formal definition of ILA, which, like the ISA, models architectural state variables and their updates in terms of instructions. It then discusses an ILA-based hardware formal verification methodology where ILA is used as a specification, and it demonstrates how formal verification can benefit from the attributes of the ILA through verification case studies. The thesis then discusses the importance of invariants in such formal hardware verification and proposes two techniques, both based on syntax-guided synthesis, forenvironment-invariant synthesis and hardware model checking, respectively. As a hardware-software interface model, ILA is also used as a hardware abstraction in system-level hardware-software verification. Specifically, as SoC components typically use shared memory accesses for bulk data transfer, the verification must take memory consistency issues into account. This is addressed by the ILA-MCM verification framework in this thesis.In summary, this thesis presents the ILA as the hardware-software interface model for the specification and verification of modern heterogeneous SoCs. The ILA-based verification methodology allows modular verification which increases the scalability of formal SoC verification.
Author | : Gabriela Nicolescu |
Publisher | : Springer Science & Business Media |
Total Pages | : 473 |
Release | : 2012-02-02 |
Genre | : Technology & Engineering |
ISBN | : 9400711255 |
Design technology to address the new and vast problem of heterogeneous embedded systems design while remaining compatible with standard “More Moore” flows, i.e. capable of simultaneously handling both silicon complexity and system complexity, represents one of the most important challenges facing the semiconductor industry today and will be for several years to come. While the micro-electronics industry, over the years and with its spectacular and unique evolution, has built its own specific design methods to focus mainly on the management of complexity through the establishment of abstraction levels, the emergence of device heterogeneity requires new approaches enabling the satisfactory design of physically heterogeneous embedded systems for the widespread deployment of such systems. Heterogeneous Embedded Systems, compiled largely from a set of contributions from participants of past editions of the Winter School on Heterogeneous Embedded Systems Design Technology (FETCH), proposes a necessarily broad and holistic overview of design techniques used to tackle the various facets of heterogeneity in terms of technology and opportunities at the physical level, signal representations and different abstraction levels, architectures and components based on hardware and software, in all the main phases of design (modeling, validation with multiple models of computation, synthesis and optimization). It concentrates on the specific issues at the interfaces, and is divided into two main parts. The first part examines mainly theoretical issues and focuses on the modeling, validation and design techniques themselves. The second part illustrates the use of these methods in various design contexts at the forefront of new technology and architectural developments.
Author | : Michael Keating, Synopsys Fellow |
Publisher | : Springer Science & Business Media |
Total Pages | : 243 |
Release | : 2011-05-17 |
Genre | : Technology & Engineering |
ISBN | : 1441985867 |
This book tackles head-on the challenges of digital design in the era of billion-transistor SoCs. It discusses fundamental design concepts in design and coding required to produce robust, functionally correct designs. It also provides specific techniques for measuring and minimizing complexity in RTL code. Finally, it discusses the tradeoff between RTL and high-level (C-based) design and how tools and languages must progress to address the needs of tomorrow’s SoC designs.
Author | : Mingsong Chen |
Publisher | : Springer Science & Business Media |
Total Pages | : 259 |
Release | : 2012-09-25 |
Genre | : Technology & Engineering |
ISBN | : 1461413591 |
This book covers state-of-the art techniques for high-level modeling and validation of complex hardware/software systems, including those with multicore architectures. Readers will learn to avoid time-consuming and error-prone validation from the comprehensive coverage of system-level validation, including high-level modeling of designs and faults, automated generation of directed tests, and efficient validation methodology using directed tests and assertions. The methodologies described in this book will help designers to improve the quality of their validation, performing as much validation as possible in the early stages of the design, while reducing the overall validation effort and cost.