Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages

Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages
Author: Yang Yi
Publisher:
Total Pages:
Release: 2011
Genre:
ISBN:
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Interconnect modeling plays an important role in design and verification of VLSI circuits and packages. For low frequency circuits, great advances for parasitic resistance and capacitance extraction have been achieved and wide varieties of techniques are available. However, for high frequency circuits and packages, parasitic inductance and impedance extraction still poses a tremendous challenge. Existing algorithms, such as FastImp and FastHenry developed by MIT, are slow and inherently unable to handle multiple dielectrics and magnetic materials. In this research, we solve three problems in interconnect modeling for high frequency circuits and packages. 1) Multiple dielectrics are common in integrated circuits and packages. We propose the first Boundary Element Method (BEM) algorithm for impedance extraction of interconnects with multiple dielectrics. The algorithm uses a novel equivalentcharge formulation to model the extraction problem with significantly fewer unknowns. Then fast matrix-vector multiplication and effective preconditioning techniques are applied to speed up the solution of linear systems. Experimental results show that the algorithm is significantly faster than existing methods with sufficient accuracy. 2) Magnetic materials are widely used in MEMS, RFID and MRAM. We present the first BEM algorithm to extract interconnect inductance with magnetic materials. The algorithm models magnetic characteristics by the Landau Lifshitz Gilbert equation and fictitious magnetic charges. The algorithm is accelerated by approximating magnetic charge effects and by modeling currents with solenoidal basis. The relative error of the algorithm with respect to the commercial tool is below 3%, while the speed is up to one magnitude faster. 3) Since traditional interconnect model includes mutual inductances between pairs of segments, the resulting circuit matrix is very dense. This has been the main bottleneck in the use of the interconnect model. Recently, K = L-1 is used. The RKC model is sparse and stable. We study the practical issues of the RKC model. We validate the RKC model and propose an efficient way to achieve high accuracy extraction by circuit simulations of practical examples.

Modeling and Simulation of High Speed VLSI Interconnects

Modeling and Simulation of High Speed VLSI Interconnects
Author: Michel S. Nakhla
Publisher: Springer Science & Business Media
Total Pages: 104
Release: 2011-06-28
Genre: Technology & Engineering
ISBN: 146152718X
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Modeling and Simulation of High Speed VLSI Interconnects brings together in one place important contributions and state-of-the-art research results in this rapidly advancing area. Modeling and Simulation of High Speed VLSI Interconnects serves as an excellent reference, providing insight into some of the most important issues in the field.

On-Chip Inductance in High Speed Integrated Circuits

On-Chip Inductance in High Speed Integrated Circuits
Author: Yehea I. Ismail
Publisher: Springer Science & Business Media
Total Pages: 310
Release: 2012-12-06
Genre: Technology & Engineering
ISBN: 1461516854
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The appropriate interconnect model has changed several times over the past two decades due to the application of aggressive technology scaling. New, more accurate interconnect models are required to manage the changing physical characteristics of integrated circuits. Currently, RC models are used to analyze high resistance nets while capacitive models are used for less resistive interconnect. However, on-chip inductance is becoming more important with integrated circuits operating at higher frequencies, since the inductive impedance is proportional to the frequency. The operating frequencies of integrated circuits have increased dramatically over the past decade and are expected to maintain the same rate of increase over the next decade, approaching 10 GHz by the year 2012. Also, wide wires are frequently encountered in important global nets, such as clock distribution networks and in upper metal layers, and performance requirements are pushing the introduction of new materials for low resistance interconnect, such as copper interconnect already used in many commercial CMOS technologies. On-Chip Inductance in High Speed Integrated Circuits deals with the design and analysis of integrated circuits with a specific focus on on-chip inductance effects. It has been described throughout this book that inductance can have a tangible effect on current high speed integrated circuits. For example, neglecting inductance and using an RC interconnect model in a production 0.25 mum CMOS technology can cause large errors (over 35%) in estimates of the propagation delay of on-chip interconnect. It has also been shown that including inductance in the repeater insertion design process as compared to using an RC model improves the overall repeater solution in terms of area, power, and delay with average savings of 40.8%, 15.6%, and 6.7%, respectively. On-Chip Inductance in High Speed Integrated Circuits is full of design and analysis techniques for RLC interconnect. These techniques are compared to techniques traditionally used for RC interconnect design to emphasize the effect of inductance. emOn-Chip Inductance in High Speed Integrated Circuits will be of interest to researchers in the area of high frequency interconnect, noise, and high performance integrated circuit design.

Compact Models and Measurement Techniques for High-Speed Interconnects

Compact Models and Measurement Techniques for High-Speed Interconnects
Author: Rohit Sharma
Publisher: Springer Science & Business Media
Total Pages: 81
Release: 2012-02-17
Genre: Technology & Engineering
ISBN: 1461410711
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Compact Models and Measurement Techniques for High-Speed Interconnects provides detailed analysis of issues related to high-speed interconnects from the perspective of modeling approaches and measurement techniques. Particular focus is laid on the unified approach (variational method combined with the transverse transmission line technique) to develop efficient compact models for planar interconnects. This book will give a qualitative summary of the various reported modeling techniques and approaches and will help researchers and graduate students with deeper insights into interconnect models in particular and interconnect in general. Time domain and frequency domain measurement techniques and simulation methodology are also explained in this book.

Compact Models and Measurement Techniques for High-Speed Interconnects

Compact Models and Measurement Techniques for High-Speed Interconnects
Author: Rohit Sharma
Publisher: Springer Science & Business Media
Total Pages: 81
Release: 2012-02-17
Genre: Technology & Engineering
ISBN: 1461410703
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Compact Models and Measurement Techniques for High-Speed Interconnects provides detailed analysis of issues related to high-speed interconnects from the perspective of modeling approaches and measurement techniques. Particular focus is laid on the unified approach (variational method combined with the transverse transmission line technique) to develop efficient compact models for planar interconnects. This book will give a qualitative summary of the various reported modeling techniques and approaches and will help researchers and graduate students with deeper insights into interconnect models in particular and interconnect in general. Time domain and frequency domain measurement techniques and simulation methodology are also explained in this book.

High-Speed VLSI Interconnections

High-Speed VLSI Interconnections
Author: Ashok K. Goel
Publisher: John Wiley & Sons
Total Pages: 433
Release: 2007-10-19
Genre: Technology & Engineering
ISBN: 0470165960
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This Second Edition focuses on emerging topics and advances in the field of VLSI interconnections In the decade since High-Speed VLSI Interconnections was first published, several major developments have taken place in the field. Now, updated to reflect these advancements, this Second Edition includes new information on copper interconnections, nanotechnology circuit interconnects, electromigration in the copper interconnections, parasitic inductances, and RLC models for comprehensive analysis of interconnection delays and crosstalk. Each chapter is designed to exist independently or as a part of one coherent unit, and several appropriate exercises are provided at the end of each chapter, challenging the reader to gain further insight into the contents being discussed. Chapter subjects include: * Preliminary Concepts * Parasitic Resistances, Capacitances, and Inductances * Interconnection Delays * Crosstalk Analysis * Electromigration-Induced Failure Analysis * Future Interconnections High-Speed VLSI Interconnections, Second Edition is an indispensable reference for high-speed VLSI designers, RF circuit designers, and advanced students of electrical engineering.

Interconnect Noise Optimization in Nanometer Technologies

Interconnect Noise Optimization in Nanometer Technologies
Author: Mohamed Elgamel
Publisher: Springer Science & Business Media
Total Pages: 145
Release: 2006-03-20
Genre: Technology & Engineering
ISBN: 0387293663
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Presents a range of CAD algorithms and techniques for synthesizing and optimizing interconnect Provides insight & intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits

Electrical Characterization and Circuit Modeling of Interconnections and Packages for High Speed Circuits by Time Domain Measurements

Electrical Characterization and Circuit Modeling of Interconnections and Packages for High Speed Circuits by Time Domain Measurements
Author: Jyh-ming Jong
Publisher:
Total Pages: 254
Release: 1995
Genre: Digital electronics
ISBN:
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With edge rates of high speed digital devices pushing into the sub-nano second range, interconnections with the associated packages play a major role in determining the speed, size and performance of digital circuits and systems. The purpose of this study is to develop experimental techniques based on time domain peeling algorithms (dynamic deconvolution) for accurate electrical characterization and circuit modeling of general interconnection structures. This thesis describes the basic principles and computational procedure of these time domain peeling algorithms, accompanied by many illustrations and examples of practical interconnection structures in high speed electronic packages. These include general single (isolated) interconnections with nonuniform cross section, general uniformly/ nonuniformly coupled interconnection structures with discontinuities, power/ ground systems with the associated parallel plane structures, resistive lossy interconnections in thin film single and multi-chip modules, and multilayer high-pin-count packages. It is shown that the distributed circuit models consisting of cascaded transmission line sections lead to an accurate evaluation of the time domain response of high speed interconnection structures. These distributed models are synthesized from the time domain reflection and transmission (TDRIT) measurements, and the impedance profiles of the distributed model are extracted by using scattering matrix-based peeling algorithms By direct time domain integration or frequency domain optimization, the distributed circuit model can also be used to construct the lumped element circuit model as well as the proposed hybrid element model consisting of transmission lines and lumped elements. The hybrid model is intended to combine the efficiency of the lumped element model with the accuracy of the distributed circuit model leading to efficient accurate simulation of circuits in general CAD tools. The accuracy of these circuit models is also confirmed by comparing the simulated data with the measured data for the test fixtures on printed circuit boards (PCBs) and chip-to-chip level interconnections. The techniques developed in this thesis can help to assure the signal fidelity of high speed circuits in the early design stage by incorporating interconnect models into integrated circuit design and simulation.