With edge rates of high speed digital devices pushing into the sub-nano second range, interconnections with the associated packages play a major role in determining the speed, size and performance of digital circuits and systems. The purpose of this study is to develop experimental techniques based on time domain peeling algorithms (dynamic deconvolution) for accurate electrical characterization and circuit modeling of general interconnection structures. This thesis describes the basic principles and computational procedure of these time domain peeling algorithms, accompanied by many illustrations and examples of practical interconnection structures in high speed electronic packages. These include general single (isolated) interconnections with nonuniform cross section, general uniformly/ nonuniformly coupled interconnection structures with discontinuities, power/ ground systems with the associated parallel plane structures, resistive lossy interconnections in thin film single and multi-chip modules, and multilayer high-pin-count packages. It is shown that the distributed circuit models consisting of cascaded transmission line sections lead to an accurate evaluation of the time domain response of high speed interconnection structures. These distributed models are synthesized from the time domain reflection and transmission (TDRIT) measurements, and the impedance profiles of the distributed model are extracted by using scattering matrix-based peeling algorithms By direct time domain integration or frequency domain optimization, the distributed circuit model can also be used to construct the lumped element circuit model as well as the proposed hybrid element model consisting of transmission lines and lumped elements. The hybrid model is intended to combine the efficiency of the lumped element model with the accuracy of the distributed circuit model leading to efficient accurate simulation of circuits in general CAD tools. The accuracy of these circuit models is also confirmed by comparing the simulated data with the measured data for the test fixtures on printed circuit boards (PCBs) and chip-to-chip level interconnections. The techniques developed in this thesis can help to assure the signal fidelity of high speed circuits in the early design stage by incorporating interconnect models into integrated circuit design and simulation.