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| Author | : 翁榆航 |
| Publisher | : |
| Total Pages | : 89 |
| Release | : 2008 |
| Genre | : |
| ISBN | : |
| Author | : Howard Cam Luong |
| Publisher | : Springer |
| Total Pages | : 214 |
| Release | : 2015-10-07 |
| Genre | : Technology & Engineering |
| ISBN | : 3319158740 |
This book provides in-depth coverage of transformer-based design techniques that enable CMOS oscillators and frequency dividers to achieve state-of-the-art performance. Design, optimization, and measured performance of oscillators and frequency dividers for different applications are discussed in detail, focusing on not only ultra-low supply voltage but also ultra-wide frequency tuning range and locking range. This book will be an invaluable reference for anyone working or interested in CMOS radio-frequency or mm-Wave integrated circuits and systems.
| Author | : Liang Dai |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 170 |
| Release | : 2012-12-06 |
| Genre | : Technology & Engineering |
| ISBN | : 1461511453 |
Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results. The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.
| Author | : Prithvi Shylendra |
| Publisher | : |
| Total Pages | : |
| Release | : 2006 |
| Genre | : Engineering |
| ISBN | : 9780542610349 |
This thesis presents the design of a new CMOS Voltage Controlled Oscillator and a frequency divider, both of which form important blocks in the design of a PLL synthesizer. These components are important because they operate at the highest frequencies within the PLL and also consume most of the power as compared to the other components. Both these circuits have been an active topic of research in recent years especially with the scaling of technology bringing hopes of complete system-on-chip (SOC) integration at RF frequencies. The circuits in this thesis are designed for 5 GHz applications, mainly for the IEEE Wireless Local Area Network (WLAN) 802.11a standard which spans the frequency range from 5.14 GHz to 5.72 GHz. The first part of the thesis is an introduction to receiver architectures, VCO's and frequency dividers in general. The second part deals with the design, analysis and simulation results of a novel VCO presented in this work. The VCO achieves a tuning range of 130 MHz around a center frequency of 5.70 GHz and a low phase noise of -114 dBc/Hz at an offset of 1 MHz. The third part presents the design approach adopted here to designing a high frequency divider using dynamic logic and its simulation results. The logic used here is True Single Phase Clocking (TSPC), which makes use of a single clock thereby avoiding the problems of clock skew and loading. Two main blocks have been presented, the divide-by-2 and divide-by-2/3. These blocks are then cascaded to achieve higher division ratios.
| Author | : Yipeng Wang |
| Publisher | : |
| Total Pages | : 89 |
| Release | : 2012 |
| Genre | : |
| ISBN | : 9781267298164 |
This thesis presents a wide-band, low phase noise, low power Quadrature Voltage Controlled Oscillator (QVCO) designed in 0.18um CMOS Silicon on Insulator (SOI) technology. The 2.4 GHz ISM band QVCO achieves -124 dBc/Hz phase noise at 1MHz offset, 25% tuning range and 2.4mW power consumption under 1.1V supply. The SOI technology facilitates the design of high performance LC-VCO. High substrate resistance of SOI enables the fabrication of high Q on-chip inductor, which significantly improves VCO's phase noise performance. Moreover, an accumulation-mode (AMOS) varactor with reduced junction parasitic in SOI widens the VCO's tuning range. The Ring Injection Locked Frequency Divider (Ring-ILFD) demonstrates its wide locking range and low power consumption in high speed application. A combination of multiple injection and direct injection technique is used in this design to further enhance the locking range. The ILFD generates quadrature signal by halving the core VCO's output while strictly following its phase noise performance.
| Author | : 郭彥宏 |
| Publisher | : |
| Total Pages | : 60 |
| Release | : 2009 |
| Genre | : |
| ISBN | : |
| Author | : Kai Zhu |
| Publisher | : |
| Total Pages | : 121 |
| Release | : 2012 |
| Genre | : |
| ISBN | : |
There has been a dramatic increase in wireless awareness among the user community in the past few years. As the wireless communication devices require more integration in terms of both hardware and software, the low-power integrated circuit (IC) solution has gained higher dedication and will dominate in the future radio-frequency IC (RFIC) design. Complementary Metal-Oxide Semiconductor (CMOS) process is extremely attractive for such applications because of its low cost and the possibility to integrate baseband and high frequency circuits on the same chip. The transceiver is often the most power-hungry block in a wireless communication system. The frequency divider (prescaler) and the voltage controlled oscillator (VCO) which are essential building blocks of in the frequency synthesizer of the transmitter are among the major sources of power consumption. This work focuses on prescalers. The injection-locked frequency dividers (ILFD) were introduced in the recent past for low-power frequency division. ILFDs can consume an order of magnitude lower power when compared to conventional flip-flop based dividers. However their range of operating frequency, also known as the locking range, is limited. ILFDs can be classified as LC tank, ring or relaxation oscillator based. There have been a lot of published works on the LC tank and ring oscillator based ILFDs. However, the one on relaxation oscillator based ILFD has been rarely reported, especially for RF applications. Besides, it is usually employed to implement a single division ratio such as 2, 3, 4 with an ILFD, while dual- or multi-moduli prescaler is more attractive to an RF synthesizer and are also rarely studied among published ILFDs. The goal of this work is to initially characterize the relaxation ILFD for RF applications. The locking range is optimized by the proposed topology. Besides, mathematical derivation is developed to verify the optimization. ILFD is also designed for different moduli with an easily controlled manner. Finally, the dual-modulus ILFD is also implemented based on the proposed structure. A prototype is fabricated in a 90-nm CMOS process and successfully tested.
| Author | : J. Craninckx |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 284 |
| Release | : 1998-04-30 |
| Genre | : Technology & Engineering |
| ISBN | : 9780792381389 |
The recent boom in the mobile telecommunication market has trapped the interest of almost all electronic and communication companies worldwide. New applications arise every day, more and more countries are covered by digital cellular systems and the competition between the several providers has caused prices to drop rapidly. The creation of this essentially new market would not have been possible without the ap pearance of smalI, low-power, high-performant and certainly low-cost mobile termi nals. The evolution in microelectronics has played a dominant role in this by creating digital signal processing (DSP) chips with more and more computing power and com bining the discrete components of the RF front-end on a few ICs. This work is situated in this last area, i. e. the study of the full integration of the RF transceiver on a single die. Furthermore, in order to be compatible with the digital processing technology, a standard CMOS process without tuning, trimming or post-processing steps must be used. This should flatten the road towards the ultimate goal: the single chip mobile phone. The local oscillator (LO) frequency synthesizer poses some major problems for integration and is the subject of this work. The first, and also the largest, part of this text discusses the design of the Voltage Controlled Oscillator (VCO). The general phase noise theory of LC-oscillators is pre sented, and the concept of effective resistance and capacitance is introduced to char acterize and compare the performance of different LC-tanks.
| Author | : Howard Cam Luong |
| Publisher | : Cambridge University Press |
| Total Pages | : 200 |
| Release | : 2004-08-26 |
| Genre | : Technology & Engineering |
| ISBN | : 1139454579 |
A frequency synthesizer is one of the most critical building blocks in any wireless transceiver system. Its design is getting more and more challenging as the demand for low-voltage low-power high-frequency wireless systems continuously grows. As the supply voltage is decreased, many existing design techniques are no longer applicable. This book provides the reader with architectures and design techniques to enable CMOS frequency synthesizers to operate at low supply voltage at high frequency with good phase noise and low power consumption. In addition to updating the reader on many of these techniques in depth, this book will also introduce useful guidelines and step-by-step procedure on behaviour simulations of frequency synthesizers. Finally, three successfully demonstrated CMOS synthesizer prototypes with detailed design consideration and description will be elaborated to illustrate potential applications of the architectures and design techniques described. For engineers, managers and researchers working in radio-frequency integrated-circuit design for wireless applications.
| Author | : George Gal |
| Publisher | : |
| Total Pages | : |
| Release | : 2013 |
| Genre | : |
| ISBN | : |
"High-frequency fractional-N PLLs in CMOS technology in the 30 to 40 GHz are very dicult to design when considering power, area, phase noise requirements and frequency range of operation. One of the diculties is to synthesize the loop lter of the PLL such that it meets the phase noise characteristics using the information available for all the components that make up the PLL. At the same time, predicting the phase noise output of the PLL using extracted layout results takes a long time to simulate and often the solution does not converge, thereby lengthening the design cycle. This thesis proposes a new methodology for designing high performance wide-band fractional-N PLLs in the 30-40 GHz range. The method begins by rst designing the phase-frequency detector/charge-pump, voltage-controlled oscillator and frequency divider circuit for realization in a specic CMOS technology. The method of choice mixes insight deemed from both a theoretical and simulation perspective. Next, the loop lter is derived based on the layout extracted behaviour of each component. Once complete, all components of the PLL are described using the high-level description language of Verilog-A available in the Cadence tool set over its full range of operating characteristics. Ideally, these components would be fabricated rst and characterized afterward. The Verilog-A description of the PLL enables a fast and ecient simulation of the complete PLL in a closed-loop conguration. This latter steps allows further optimization of the overall design. Two chips have been fabricated; one in a 0.13 m CMOS process from IBM and another in a 65 nm CMOS process from TSMC. One chip contain the design of a 28 GHz VCO and another containing the design of a programmable frequency divider circuit. Experimental results for both chip are provided." --
