Secure computing is gaining importance in recent times as computing capability is increasingly becoming distributed and information is everywhere. Prevention of piracy and digital rights management has become very important. Information security is mandatory rather than an additional feature. Numerous software techniques have been proposed to provide certain level of copyright and intellectual property protection. Techniques like obfuscation attempt to transform the code into a form that is harder to reverse engineer. Tamper-proofing causes a program to malfunction when it detects that it has been modified. Software watermarking embeds copyright notice in the software code to allow the owners of the software to assert their intellectual property rights. The software techniques discourage software theft, can trace piracy, prove ownership, but cannot prevent copying itself. Thus, software based security firewalls and encryption is not completely safe from determined hackers. This necessitates the need for information security at the hardware level, where secure processors assume importance. In this dissertation, a detailed architecture and instruction set of the SCAN-Secure Processor is proposed. The SCAN-SP is a modified SparcV8 processor architecture with a new instruction set to handle image compression, encryption, information hiding based on SCAN methodology and biometric authentication based on Local Global Graph methodology. A SCAN based methodology for encryption and decryption of 32 bit instructions and data is proposed. The modules to support the new instructions are synthesized in reconfigurable logic and the results of FPGA synthesis are presented. The ultimate goal of the proposed work is a detailed study of the tradeoffs that exists between speed of execution and security of the processor. Designing a faster processor is not the goal of the proposed work, rather exploring the architecture to provide security is of prime importance.