Characterization and Implementation of an Injection Locked Frequency Divider Based on Relaxation Oscillator

Characterization and Implementation of an Injection Locked Frequency Divider Based on Relaxation Oscillator
Author: Kai Zhu
Publisher:
Total Pages: 121
Release: 2012
Genre:
ISBN:

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There has been a dramatic increase in wireless awareness among the user community in the past few years. As the wireless communication devices require more integration in terms of both hardware and software, the low-power integrated circuit (IC) solution has gained higher dedication and will dominate in the future radio-frequency IC (RFIC) design. Complementary Metal-Oxide Semiconductor (CMOS) process is extremely attractive for such applications because of its low cost and the possibility to integrate baseband and high frequency circuits on the same chip. The transceiver is often the most power-hungry block in a wireless communication system. The frequency divider (prescaler) and the voltage controlled oscillator (VCO) which are essential building blocks of in the frequency synthesizer of the transmitter are among the major sources of power consumption. This work focuses on prescalers. The injection-locked frequency dividers (ILFD) were introduced in the recent past for low-power frequency division. ILFDs can consume an order of magnitude lower power when compared to conventional flip-flop based dividers. However their range of operating frequency, also known as the locking range, is limited. ILFDs can be classified as LC tank, ring or relaxation oscillator based. There have been a lot of published works on the LC tank and ring oscillator based ILFDs. However, the one on relaxation oscillator based ILFD has been rarely reported, especially for RF applications. Besides, it is usually employed to implement a single division ratio such as 2, 3, 4 with an ILFD, while dual- or multi-moduli prescaler is more attractive to an RF synthesizer and are also rarely studied among published ILFDs. The goal of this work is to initially characterize the relaxation ILFD for RF applications. The locking range is optimized by the proposed topology. Besides, mathematical derivation is developed to verify the optimization. ILFD is also designed for different moduli with an easily controlled manner. Finally, the dual-modulus ILFD is also implemented based on the proposed structure. A prototype is fabricated in a 90-nm CMOS process and successfully tested.

Reconfigurable Dual-mode Voltage-controlled Oscillator and Wideband Frequency Synthesizer for Millimeter-wave Applications

Reconfigurable Dual-mode Voltage-controlled Oscillator and Wideband Frequency Synthesizer for Millimeter-wave Applications
Author: Cheng-Hsien Hung
Publisher:
Total Pages: 260
Release: 2015
Genre:
ISBN:

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Demands for high data-rate communications and high-precision sensing applications have pushed wireless systems towards higher operating frequencies where wider bandwidth is available. Examples of such applications include 60 GHz indoor communications and vehicular RADAR around 77 GHz. High-speed frequency synthesizers integrated in a CMOS process, with wide operating bandwidth, and low phase noise are key to low-cost transceiver implementations for such applications. The requirement to operate over a wide span of carrier frequencies arises from two key sources. The system itself often requires a wide tuning range, in excess of 5-10% of the carrier frequency. Further, it is necessary to compensate for the uncertainty in operating frequencies, caused by process and temperature variations. This dissertation introduces a dual-mode voltage-controlled oscillator (VCO) topology, embedded in a frequency synthesizer, for wideband operation. The VCO can operate in two oscillation modes by reconfiguring the active negative resistance core around the LC tank that is employed as the resonator element in the oscillator. A key aspect to the design is that the switches used for mode reconfiguration do not contribute to the tank loss. The frequency spacing of the two modes is determined by an accurate inductor ratio. It is demonstrated through analysis that in order to ensure mode-switching, the size of the switches needs be larger than a critical value, which is a function of the electrical properties of the cross-coupled, negative resistance core, as well as the resonator used in the design. The impact of noise injection and mismatch on switching behavior is also analyzed. The VCO topology has been implemented in a 65nm CMOS process. The design demonstrates measured tuning ranges of 56.9 GHz to 65.4 GHz, and 64.6 GHz to 75.3 GHz, in the two respective modes, for a total effective tuning range of 28%. The oscillator consumes 13 mW, with a 1 V-supply, and its Figure of Merit with tuning range (FOM[subscript T]) is -177.2 dB. An integer-N frequency synthesizer that employs the dual-mode VCO, has also been designed and verified in a 65 nm CMOS process. The synthesizer has a locking range from 56 GHz to 63.9 GHz in its low frequency mode. The total power consumption of the synthesizer, including output buffers, is approximately 50 mW. The in-band phase noise, at a locked frequency of 63.04 GHz, is -88.4 dBc/Hz at 1 MHz offset.

A 3.8-6.4GHz Local Oscillator System Using an Injection-Locked Frequency Doubling and Phase Tuning Technique

A 3.8-6.4GHz Local Oscillator System Using an Injection-Locked Frequency Doubling and Phase Tuning Technique
Author: James P. Maligeorgos
Publisher:
Total Pages:
Release: 2001
Genre:
ISBN:

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This thesis studies the design of a novel local oscillator system based on low-voltage and low-power regenerative (injection locking) techniques. The LO system converts an input signal of frequeney 'fLO'/2 into a quadrature pair of LO signals at a frequency of 'fLO', intended to drive a pair of I and Q down-converting mixers. A new IC compatible technique for regenerative frequency doubling is presented. Regenerative frequency doublers are cascaded on-chip to provide a net multiply-by-4 function, generating frequencies in excess of fT2 without the need for interstage filtering. A new technique is also presented for frequency-independent phase control of the quadrature LO signals of a regenerative divider (I-Q generator), achieving a precision on the order of 0.01°. Results are presented in the context of a fabricated 5-6GHz image reject receiver.

All-Digital Frequency Synthesizer in Deep-Submicron CMOS

All-Digital Frequency Synthesizer in Deep-Submicron CMOS
Author: Robert Bogdan Staszewski
Publisher: John Wiley & Sons
Total Pages: 281
Release: 2006-09-22
Genre: Technology & Engineering
ISBN: 0470041943

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A new and innovative paradigm for RF frequency synthesis and wireless transmitter design Learn the techniques for designing and implementing an all-digital RF frequency synthesizer. In contrast to traditional RF techniques, this innovative book sets forth digitally intensive design techniques that lead the way to the development of low-cost, low-power, and highly integrated circuits for RF functions in deep submicron CMOS processes. Furthermore, the authors demonstrate how the architecture enables readers to integrate an RF front-end with the digital back-end onto a single silicon die using standard ASIC design flow. Taking a bottom-up approach that progressively builds skills and knowledge, the book begins with an introduction to basic concepts of frequency synthesis and then guides the reader through an all-digital RF frequency synthesizer design: Chapter 2 presents a digitally controlled oscillator (DCO), which is the foundation of a novel architecture, and introduces a time-domain model used for analysis and VHDL simulation Chapter 3 adds a hierarchical layer of arithmetic abstraction to the DCO that makes it easier to operate algorithmically Chapter 4 builds a phase correction mechanism around the DCO such that the system's frequency drift or wander performance matches that of the stable external frequency reference Chapter 5 presents an application of the all-digital RF synthesizer Chapter 6 describes the behavioral modeling and simulation methodology used in design The final chapter presents the implementation of a full transmitter and experimental results. The novel ideas presented here have been implemented and proven in two high-volume, commercial single-chip radios developed at Texas Instruments: Bluetooth and GSM. While the focus of the book is on RF frequency synthesizer design, the techniques can be applied to the design of other digitally assisted analog circuits as well. This book is a must-read for students and engineers who want to learn a new paradigm for RF frequency synthesis and wireless transmitter design using digitally intensive design techniques.

Low-power Low-phase-noise Voltage-controlled Oscillator Design

Low-power Low-phase-noise Voltage-controlled Oscillator Design
Author: Yue Yu
Publisher:
Total Pages: 230
Release: 2006
Genre: Oscillators, Electric
ISBN:

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Abstract: The design of voltage-controlled Oscillators nowadays is all about being capable of operating at higher clock frequencies for the purpose of higher data rate, consuming less power for the purpose of longer battery life, and having better phase noise performance for the purpose of higher quality of wireless service and more efficient use of the available frequency spectrum since most of the wireless and mobile terminals that these VCOs work in are required to be able to operate in multiple RF standards to serve new generations of standards while being backward compatible with existing ones, leading to a demand for multi-standard multi-band radio operation that deals with high frequency RF signals that undergo different modulation schemes of different standards in different channels over a wide range of frequency band. A top-down system design from the PLL to the VCO is carried out to determine the specifications for a fully integrated dual-band voltage-controlled oscillator (VCO) designed for a Zero-IF WiMAX/WLAN receiver in a O.18tm CMOS technology with 1.8V supply voltage. A VCO employing a differential cross-coupled inductance-capacitance (LC) tank architecture is proposed to cover twice the desired frequency bands for WiMAX and WLAN standards in order to avoid load pulling between VCO frequency and incoming RF frequency. The switching between two bands is implemented by using two binary-weighted capacitor arrays while switching inside each sub-band is implemented by different digital control signal combinations for the binary-weighted capacitances. A phase noise of -120.7dB/Hz at 1MHz offset frequency is demonstrated for an oscillation frequency of 4.84GHz. The average power consumption of this VCO is 8.1mW. This VCO is developed as an IP (Intellectual Property) to be used in a fully integrated CMOS multi-standard WiMAX/WLAN radio allowing seamless roaming of handheld mobile devices between hotspots in future Wireless Metropolitan Area Network (WMAN). To compare the performance of ring oscillators to that of LC tank oscillators, the designs of two three-stage multiple-pass voltage-controlled ring oscillators with dual-delay paths are demonstrated where the differential delay cell utilizes both the primary loop delay and the negative skewed delay to increase the frequency of oscillation substantially and retain or even increase tuning range. Their phase noise performance is also improved by switching in and out the transistors periodically. In design I, the covered frequency range is from 0.74 GHz to 1.96 GHz, which translates to a tuning range of 90 % A phase noise of -104.995dBc/Hz is demonstrated for an oscillation frequency of 1.8535 GHz. Each stage draws a current of 4.963mA on average from a 1.8V power supply, resulting in a power consumption of 26.8mW. In design II, the covered frequency range is from 1.0478 GHz to 2.0022 GHz, which translates to a tuning range of 63%. The frequency-voltage curve is almost a perfect linear curve for V between OV and 0.9V. A phase noise of -110.O45dBc/Hz is demonstrated for an oscillation frequency of 2.00216 GHz. Each stage draws a current of 10.179mA on average from a 1.8V power supply, resulting in a power consumption of 55mW.