Gallium Nitride (GaN) and related alloys have gained considerable momentum in recent years since the improvement in silicon (Si) based power devices is now only incremental. GaN is a promising material for high-power, high-frequency applications due to its wide bandgap, high carrier mobility which result in devices with high breakdown voltage, low on-resistance, and high temperature stability. Despite the superior properties of GaN there is still room for improvement in device design and fabrication to reach theoretical limits of GaN based devices. Reaching the theoretical critical electric field in GaN devices has been challenging due to the presence of threading dislocations, surface impurities introduced during material growth and fabrication process. In order to prevent premature breakdown of the devices, these defects must be mitigated. In this study, avalanche breakdown was observed in p-n diodes fabricated with low power reactive ion etch with a moat etch profile, followed by Mg ion implantation to passivate the plasma damages. Additionally, the devices were fabricated on free standing GaN substrates which has lower dislocation than sapphire or SiC substrates. The electron and hole impact ionization coefficients were extracted separately by analyzing the ultraviolet (UV) assisted reverse bias current voltage measurements of vertical p-n and n-p diodes. GaN and related alloy such as Indium Aluminum Nitride (InAlN) or Aluminum Gallium Nitride (AlGaN) form a high mobility, high density sheet charge at the heterojunction. High electron mobility transistor (HEMT) devices fabricated on these layer stacks are depletion mode (normally-on) devices with a negative threshold voltage. However, normally-on devices are not preferred in power applications due to safety reasons and to reduce the external circuitry. Therefore, the development of an enhancement mode (normally-off) GaN based high electron mobility transistors (HEMT) with positive threshold voltage is important for next generation power devices. Several methods, such as growing a p-GaN on the barrier layer, recessed gate by dry etching, plasma treatment under the gate have been previously studied to develop enhancement-mode HEMT devices. In this study, MOS-HEMT devices were fabricated by selective thermal oxidation of InAlN to reduce InAlN barrier thickness under the gate contact. The thermal oxidation of InAlN occurs at temperatures above 600°C, while GaN oxidation occurs above 1000°C at a slow rate which allows the decrease of the InAlN barrier layer thickness under the gate in a reliable way due to the self-limiting nature of oxidation. A positive shift in the threshold voltage and a reduction in reverse leakage current was demonstrated on MOS-diode structures by thermally oxidizing InAlN layers with In composition of 0.17, 0.178 and 0.255 for increasing oxidation durations at 700°C and 800°C. Enhancement mode device operation was demonstrated on lattice matched InAlN/AlN/GaN/Sapphire MOS-HEMT devices by selective thermal oxidation of InAlN layer under the gate contact. A positive threshold voltage was observed for devices which were subjected to thermal oxidation at 700°C for 10, 30 and 60 minutes. The highest threshold voltage was observed as 1.16 V for the device that was oxidized for 30 minutes at 700°C. The maximum transconductance and the maximum drain saturation current of this device was 4.27 mS/mm and 150 mA/mm, respectively.