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| Author | : Jonghwan Lee |
| Publisher | : |
| Total Pages | : 414 |
| Release | : 2003 |
| Genre | : Electronic circuits |
| ISBN | : |
| Author | : Francis Balestra |
| Publisher | : John Wiley & Sons |
| Total Pages | : 518 |
| Release | : 2013-03-01 |
| Genre | : Technology & Engineering |
| ISBN | : 1118622472 |
This book provides a comprehensive review of the state-of-the-art in the development of new and innovative materials, and of advanced modeling and characterization methods for nanoscale CMOS devices. Leading global industry bodies including the International Technology Roadmap for Semiconductors (ITRS) have created a forecast of performance improvements that will be delivered in the foreseeable future – in the form of a roadmap that will lead to a substantial enlargement in the number of materials, technologies and device architectures used in CMOS devices. This book addresses the field of materials development, which has been the subject of a major research drive aimed at finding new ways to enhance the performance of semiconductor technologies. It covers three areas that will each have a dramatic impact on the development of future CMOS devices: global and local strained and alternative materials for high speed channels on bulk substrate and insulator; very low access resistance; and various high dielectric constant gate stacks for power scaling. The book also provides information on the most appropriate modeling and simulation methods for electrical properties of advanced MOSFETs, including ballistic transport, gate leakage, atomistic simulation, and compact models for single and multi-gate devices, nanowire and carbon-based FETs. Finally, the book presents an in-depth investigation of the main nanocharacterization techniques that can be used for an accurate determination of transport parameters, interface defects, channel strain as well as RF properties, including capacitance-conductance, improved split C-V, magnetoresistance, charge pumping, low frequency noise, and Raman spectroscopy.
| Author | : Chung-Hsun Lin |
| Publisher | : |
| Total Pages | : 370 |
| Release | : 2007 |
| Genre | : |
| ISBN | : |
| Author | : Josef Sikula |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 371 |
| Release | : 2006-02-21 |
| Genre | : Technology & Engineering |
| ISBN | : 1402021704 |
A discussion of recently developed experimental methods for noise research in nanoscale electronic devices, conducted by specialists in transport and stochastic phenomena in nanoscale physics. The approach described is to create methods for experimental observations of noise sources, their localization and their frequency spectrum, voltage-current and thermal dependences. Our current knowledge of measurement methods for mesoscopic devices is summarized to identify directions for future research, related to downscaling effects. The directions for future research into fluctuation phenomena in quantum dot and quantum wire devices are specified. Nanoscale electronic devices will be the basic components for electronics of the 21st century. From this point of view the signal-to-noise ratio is a very important parameter for the device application. Since the noise is also a quality and reliability indicator, experimental methods will have a wide application in the future.
| Author | : Sandeep K. Goel |
| Publisher | : CRC Press |
| Total Pages | : 259 |
| Release | : 2017-12-19 |
| Genre | : Technology & Engineering |
| ISBN | : 143982942X |
Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits covers common problems in areas such as process variations, power supply noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DfM)-related rule violations. The book also addresses testing for small-delay defects (SDDs), which can cause immediate timing failures on both critical and non-critical paths in the circuit. Overviews semiconductor industry test challenges and the need for SDD testing, including basic concepts and introductory material Describes algorithmic solutions incorporated in commercial tools from Mentor Graphics Reviews SDD testing based on "alternative methods" that explores new metrics, top-off ATPG, and circuit topology-based solutions Highlights the advantages and disadvantages of a diverse set of metrics, and identifies scope for improvement Written from the triple viewpoint of university researchers, EDA tool developers, and chip designers and tool users, this book is the first of its kind to address all aspects of SDD testing from such a diverse perspective. The book is designed as a one-stop reference for current industrial practices, research challenges in the domain of SDD testing, and recent developments in SDD solutions.
| Author | : |
| Publisher | : |
| Total Pages | : |
| Release | : 2018 |
| Genre | : |
| ISBN | : |
| Author | : Samar K. Saha |
| Publisher | : CRC Press |
| Total Pages | : 385 |
| Release | : 2018-09-03 |
| Genre | : Technology & Engineering |
| ISBN | : 1351831070 |
Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond provides a modern treatise on compact models for circuit computer-aided design (CAD). Written by an author with more than 25 years of industry experience in semiconductor processes, devices, and circuit CAD, and more than 10 years of academic experience in teaching compact modeling courses, this first-of-its-kind book on compact SPICE models for very-large-scale-integrated (VLSI) chip design offers a balanced presentation of compact modeling crucial for addressing current modeling challenges and understanding new models for emerging devices. Starting from basic semiconductor physics and covering state-of-the-art device regimes from conventional micron to nanometer, this text: Presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models Discusses the major issue of process variability, which severely impacts device and circuit performance in advanced technologies and requires statistical compact models Promotes further research of the evolution and development of compact models for VLSI circuit design and analysis Supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices Includes exercise problems at the end of each chapter and extensive references at the end of the book Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond is intended for senior undergraduate and graduate courses in electrical and electronics engineering as well as for researchers and practitioners working in the area of electron devices. However, even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts from this book.
| Author | : Tibor Grasser |
| Publisher | : Springer Nature |
| Total Pages | : 724 |
| Release | : 2020-04-26 |
| Genre | : Technology & Engineering |
| ISBN | : 3030375005 |
This book summarizes the state-of-the-art, regarding noise in nanometer semiconductor devices. Readers will benefit from this leading-edge research, aimed at increasing reliability based on physical microscopic models. Authors discuss the most recent developments in the understanding of point defects, e.g. via ab initio calculations or intricate measurements, which have paved the way to more physics-based noise models which are applicable to a wider range of materials and features, e.g. III-V materials, 2D materials, and multi-state defects. Describes the state-of-the-art, regarding noise in nanometer semiconductor devices; Enables readers to design more reliable semiconductor devices; Offers the most up-to-date information on point defects, based on physical microscopic models.
| Author | : Gennady Gildenblat |
| Publisher | : Springer Science & Business Media |
| Total Pages | : 531 |
| Release | : 2010-06-22 |
| Genre | : Technology & Engineering |
| ISBN | : 9048186145 |
Most of the recent texts on compact modeling are limited to a particular class of semiconductor devices and do not provide comprehensive coverage of the field. Having a single comprehensive reference for the compact models of most commonly used semiconductor devices (both active and passive) represents a significant advantage for the reader. Indeed, several kinds of semiconductor devices are routinely encountered in a single IC design or in a single modeling support group. Compact Modeling includes mostly the material that after several years of IC design applications has been found both theoretically sound and practically significant. Assigning the individual chapters to the groups responsible for the definitive work on the subject assures the highest possible degree of expertise on each of the covered models.
| Author | : Soumya Pandit |
| Publisher | : CRC Press |
| Total Pages | : 410 |
| Release | : 2018-09-03 |
| Genre | : Technology & Engineering |
| ISBN | : 1351831992 |
Reliability concerns and the limitations of process technology can sometimes restrict the innovation process involved in designing nano-scale analog circuits. The success of nano-scale analog circuit design requires repeat experimentation, correct analysis of the device physics, process technology, and adequate use of the knowledge database. Starting with the basics, Nano-Scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design introduces the essential fundamental concepts for designing analog circuits with optimal performances. This book explains the links between the physics and technology of scaled MOS transistors and the design and simulation of nano-scale analog circuits. It also explores the development of structured computer-aided design (CAD) techniques for architecture-level and circuit-level design of analog circuits. The book outlines the general trends of technology scaling with respect to device geometry, process parameters, and supply voltage. It describes models and optimization techniques, as well as the compact modeling of scaled MOS transistors for VLSI circuit simulation. • Includes two learning-based methods: the artificial neural network (ANN) and the least-squares support vector machine (LS-SVM) method • Provides case studies demonstrating the practical use of these two methods • Explores circuit sizing and specification translation tasks • Introduces the particle swarm optimization technique and provides examples of sizing analog circuits • Discusses the advanced effects of scaled MOS transistors like narrow width effects, and vertical and lateral channel engineering Nano-Scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design describes the models and CAD techniques, explores the physics of MOS transistors, and considers the design challenges involving statistical variations of process technology parameters and reliability constraints related to circuit design.
