There has been a dramatic increase in wireless awareness among the user community in the past few years. As the wireless communication devices require more integration in terms of both hardware and software, the low-power integrated circuit (IC) solution has gained higher dedication and will dominate in the future radio-frequency IC (RFIC) design. Complementary Metal-Oxide Semiconductor (CMOS) process is extremely attractive for such applications because of its low cost and the possibility to integrate baseband and high frequency circuits on the same chip. The transceiver is often the most power-hungry block in a wireless communication system. The frequency divider (prescaler) and the voltage controlled oscillator (VCO) which are essential building blocks of in the frequency synthesizer of the transmitter are among the major sources of power consumption. This work focuses on prescalers. The injection-locked frequency dividers (ILFD) were introduced in the recent past for low-power frequency division. ILFDs can consume an order of magnitude lower power when compared to conventional flip-flop based dividers. However their range of operating frequency, also known as the locking range, is limited. ILFDs can be classified as LC tank, ring or relaxation oscillator based. There have been a lot of published works on the LC tank and ring oscillator based ILFDs. However, the one on relaxation oscillator based ILFD has been rarely reported, especially for RF applications. Besides, it is usually employed to implement a single division ratio such as 2, 3, 4 with an ILFD, while dual- or multi-moduli prescaler is more attractive to an RF synthesizer and are also rarely studied among published ILFDs. The goal of this work is to initially characterize the relaxation ILFD for RF applications. The locking range is optimized by the proposed topology. Besides, mathematical derivation is developed to verify the optimization. ILFD is also designed for different moduli with an easily controlled manner. Finally, the dual-modulus ILFD is also implemented based on the proposed structure. A prototype is fabricated in a 90-nm CMOS process and successfully tested.