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| Author | : Harikumar Gopinathannair |
| Publisher | : |
| Total Pages | : 210 |
| Release | : 2004 |
| Genre | : |
| ISBN | : |
| Author | : E. Aykut Dengi |
| Publisher | : |
| Total Pages | : 125 |
| Release | : 1997 |
| Genre | : Boundary value problems |
| ISBN | : |
Abstract: "Accurate interconnect modeling has become critical for the verification and analysis of VLSI circuits with decreasing feature sizes. Capacitance extraction is a critical step in interconnect modeling. In this thesis, we present a hierarchical 2-D capacitance extraction method for VLSI circuits. The method uses a geometrical hierarchical partitioning on the 2-D vertical cross-section of a VLSI circuit. These partitions are characterized at their interfaces by macromodel capacitance matrices which can be combined to yield a global capacitance matrix for a given set of conductors or the coupling capacitance values for a given conductor. A library of such macromodels which is sufficient to describe any vertical cross section for a given technology is built as a pre-processing step to improve runtime extraction efficiency. Irregular conductor geometries as well as conformal dielectrics are handled at the preprocessing stage, enhancing runtime efficiency without affecting accuracy. We demonstrate that partitioning incurs significant errors unless special care is taken. We introduce two new boundary condition types, 'full' and 'empty', and using them established the tightest possible bounds on the error due to boundary conditions. We implement these new bounary conditions as termination macromodels and use them to expand the problem domain adaptively until a given error criterion is satisfied."
| Author | : Wenjian Yu |
| Publisher | : Springer |
| Total Pages | : 0 |
| Release | : 2016-09-03 |
| Genre | : Technology & Engineering |
| ISBN | : 9783662510223 |
Resistance and capacitance (RC) extraction is an essential step in modeling the interconnection wires and substrate coupling effect in nanometer-technology integrated circuits (IC). The field-solver techniques for RC extraction guarantee the accuracy of modeling, and are becoming increasingly important in meeting the demand for accurate modeling and simulation of VLSI designs. Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits presents a systematic introduction to, and treatment of, the key field-solver methods for RC extraction of VLSI interconnects and substrate coupling in mixed-signal ICs. Various field-solver techniques are explained in detail, with real-world examples to illustrate the advantages and disadvantages of each algorithm. This book will benefit graduate students and researchers in the field of electrical and computer engineering as well as engineers working in the IC design and design automation industries. Dr. Wenjian Yu is an Associate Professor at the Department of Computer Science and Technology at Tsinghua University in China; Dr. Xiren Wang is a R&D Engineer at Cadence Design Systems in the USA.
| Author | : Wenjian Yu |
| Publisher | : Springer Science & Business |
| Total Pages | : 258 |
| Release | : 2014-04-21 |
| Genre | : Technology & Engineering |
| ISBN | : 3642542980 |
Resistance and capacitance (RC) extraction is an essential step in modeling the interconnection wires and substrate coupling effect in nanometer-technology integrated circuits (IC). The field-solver techniques for RC extraction guarantee the accuracy of modeling, and are becoming increasingly important in meeting the demand for accurate modeling and simulation of VLSI designs. Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits presents a systematic introduction to, and treatment of, the key field-solver methods for RC extraction of VLSI interconnects and substrate coupling in mixed-signal ICs. Various field-solver techniques are explained in detail, with real-world examples to illustrate the advantages and disadvantages of each algorithm. This book will benefit graduate students and researchers in the field of electrical and computer engineering as well as engineers working in the IC design and design automation industries. Dr. Wenjian Yu is an Associate Professor at the Department of Computer Science and Technology at Tsinghua University in China; Dr. Xiren Wang is a R&D Engineer at Cadence Design Systems in the USA.
| Author | : Wenjian Yu |
| Publisher | : Springer Nature |
| Total Pages | : 262 |
| Release | : 2022-09-02 |
| Genre | : Technology & Engineering |
| ISBN | : 9811932506 |
The Monte Carlo method is one of the top 10 algorithms in the 20th century. This book is focusing on the Monte Carlo method for solving deterministic partial differential equations (PDEs), especially its application to electronic design automation (EDA) problems. Compared with the traditional method, the Monte Carlo method is more efficient when point values or linear functional of the solution are needed, and has the advantages on scalability, parallelism, and stability of accuracy. This book presents a systematic introduction to the Monte Carlo method for solving major kinds of PDEs, and the detailed explanation of relevant techniques for EDA problems especially the cutting-edge algorithms of random walk based capacitance extraction. It includes about 100 figures and 50 tables, and brings the reader a close look to the newest research results and the sophisticated algorithmic skills in Monte Carlo simulation software.
| Author | : Yu-Chung Hsiao (S.M.) |
| Publisher | : |
| Total Pages | : 65 |
| Release | : 2010 |
| Genre | : |
| ISBN | : |
State-of-the-art capacitance extraction methods for Integrated Circuits (IC) involve scanning 2D cross-sections, and interpolating 2D capacitance values using a table lookup approach. This approach is fast and accurate for a large percentage of IC wires. It is however quite inaccurate for full 3D structures, such as crossing wires in adjacent metal layers. For such cases electrostatic field solvers are required. Unfortunately standard field solvers are inherently very time-consuming, making them completely impractical in typical IC design flows. Even fast matrix-vector product approaches (e.g., fastmultipole or precorrected FFT) are inefficient for these structures since they have a significant computational overhead and scale linearly with the number of conductors only for much larger structures with more than several hundreds of wires. In this talk we present therefore a new 3D extraction field solver that is extremely efficient in particular for the smaller scale extraction problem involving the ten to one hundred conductors in the 3D structures that cannot be handled by the 2D scanning and table look up approach. Because of highly restrictive design rules of the recent sub-micro to nano-scale IC technologies, smooth and regular charge distributions extracted from simple model structures can be stored beforehand as "templates" and instantiated and stretched to fit practical complicated cases as basis function building blocks. This "template-instantiated" strategy largely reduces the number of unknowns and computational time without additional overhead. Given that all basis functions are obtained by the same very few stretched templates, Galerkin coefficients can be readily computed from a mixture of analytical, numerical and table lookup approaches. Furthermore, given the low accuracy (i.e., 3%-5%) required by IC extraction and the specific aspect ratios and separations of wires on ICs, we have observed in our numerical experimentations that edge and corner charge singularities do not need to be included in our templates, hence reducing the complexity of our solver even further.
| Author | : Prasad S. Sumant |
| Publisher | : |
| Total Pages | : |
| Release | : 2010 |
| Genre | : |
| ISBN | : |
Interconnects are an important constituent of any large scale integrated circuit, and accurate interconnect analysis is essential not only for post-layout verification but also for synthesis. For instance, extraction of interconnect capacitance is needed for the prediction of interconnect-induced delay, crosstalk, and other signal distortion related effects that are used to guide IC routing and floor planning. The continuous progress of semiconductor technology is leading ICs to the era of 45 nm technology and beyond. However, this progress has been associated with increasing variability during the manufacturing processes. This variability leads to stochastic variations in geometric and material parameters and has a significant impact on interconnect capacitance. It is therefore important to be able to quantify the effect of such process induced variations on interconnect capacitance. In this thesis, we have worked on a methodology towards modeling of interconnect capacitance in the presence of geometric uncertainties. More specifically, a methodology is proposed for the finite element solution of Laplace's equation for the calculation of the per-unit-length capacitance matrix of a multi-conductor interconnect structure embedded in a multi-layered insulating substrate and in the presence of statistical variation in conductor and substrate geometry. The proposed method is founded on the idea of defining a single, mean geometry, which is subsequently used with a single finite element discretization, to extract the statistics of the interconnect capacitance in an expedient fashion. We demonstrate the accuracy and efficiency of our method through its application to the extraction of capacitances in some representative geometries for IC interconnects.
| Author | : Indira Gazula |
| Publisher | : |
| Total Pages | : 116 |
| Release | : 2004 |
| Genre | : |
| ISBN | : |
| Author | : Yang Yi |
| Publisher | : |
| Total Pages | : |
| Release | : 2011 |
| Genre | : |
| ISBN | : |
Interconnect modeling plays an important role in design and verification of VLSI circuits and packages. For low frequency circuits, great advances for parasitic resistance and capacitance extraction have been achieved and wide varieties of techniques are available. However, for high frequency circuits and packages, parasitic inductance and impedance extraction still poses a tremendous challenge. Existing algorithms, such as FastImp and FastHenry developed by MIT, are slow and inherently unable to handle multiple dielectrics and magnetic materials. In this research, we solve three problems in interconnect modeling for high frequency circuits and packages. 1) Multiple dielectrics are common in integrated circuits and packages. We propose the first Boundary Element Method (BEM) algorithm for impedance extraction of interconnects with multiple dielectrics. The algorithm uses a novel equivalentcharge formulation to model the extraction problem with significantly fewer unknowns. Then fast matrix-vector multiplication and effective preconditioning techniques are applied to speed up the solution of linear systems. Experimental results show that the algorithm is significantly faster than existing methods with sufficient accuracy. 2) Magnetic materials are widely used in MEMS, RFID and MRAM. We present the first BEM algorithm to extract interconnect inductance with magnetic materials. The algorithm models magnetic characteristics by the Landau Lifshitz Gilbert equation and fictitious magnetic charges. The algorithm is accelerated by approximating magnetic charge effects and by modeling currents with solenoidal basis. The relative error of the algorithm with respect to the commercial tool is below 3%, while the speed is up to one magnitude faster. 3) Since traditional interconnect model includes mutual inductances between pairs of segments, the resulting circuit matrix is very dense. This has been the main bottleneck in the use of the interconnect model. Recently, K = L-1 is used. The RKC model is sparse and stable. We study the practical issues of the RKC model. We validate the RKC model and propose an efficient way to achieve high accuracy extraction by circuit simulations of practical examples.
| Author | : VLSI Society of India |
| Publisher | : Institute of Electrical & Electronics Engineers(IEEE) |
| Total Pages | : 682 |
| Release | : 1999 |
| Genre | : Computers |
| ISBN | : 9780769500133 |
The proceedings of the January 1999 conference consist of 103 papers, 11 talks, and six tutorials. The papers are grouped under the headings of TCAD to ECAD, low power, testing, co-design and synthesis, analog design, multi-valued logic, verification, digital signal processor (DSP), logic synthesis,
