Technological advances have allowed the continuous improvement of modern electronic systems. Enabled by the scaling of technology nodes, current integrated circuits are becoming increasingly complex. These intricate designs require EDA tools to ensure the rapid creation of complex new-generation architectures. Traditionally, a hardware IC design engineer designs the chips with the help of RTL language like Verilog, VHDL, or System Verilog. However, creating chips using RTL descriptions becomes challenging for the new generation of complex architectures addressing applications like deep learning and computer vision. As a result, designers nowadays use high-level languages like C/C++ or System C to design the chips. The design flows consist of multiple stages, from C-synthesis (converting C/C++ code to RTL code) to place and route. Each step is highly time-consuming, and the performance of each stage is very much dependent on the characteristics of the previous stage. The use of machine learning (ML) to help speed up electronic system design is becoming prevalent across the industry. This dissertation is a fusion of ML and EDA tools. We have solved multiple electronic design automation (EDA) problems for field-programmable gate arrays (FPGAs) technology. This dissertation applied ML to solve five significant FPGA physical design automation problems. Design closure in general VLSI physical design flows, and FPGA physical design flows are important and time-consuming problems. Routing can consume as much as 70% of the total design time. The first contribution in the dissertation is a machine learning-based post route routing congestion estimation tool, where we applied regression models on post placed FPGA netlist. Limited availability of training data is one of the significant challenges researchers face in applied machine learning in EDA flow. Therefore, training data quality and quantity play an essential role in the generated model in any machine learning application. The second contribution we addressed in this dissertation is to propose a methodology to create vast training design sets from a single HLS code. Highlevel synthesis (HLS) tools allow designers to prototype ideas on various FPGAs and ASIC platforms quickly. However, the Quality of Results (QoR) reported after HLS synthesis is highly inaccurate. This suboptimal QoR may result in false-positive closure of timing and area, which may not close after routing. The third contribution addressed in this dissertation is a robust ML-based design flow that can accurately predict post-route QoR for a given behavioral description without the need to synthesize the design. The fourth contribution of this dissertation is a generalized resource and performance estimation model for convolution neural network (CNN) architecture. Design space exploration (DSE) of HLS designs is the process of finding a set of optimized designs for area and performance. Traditional DSE is time-consuming, and the resulting design points are not always optimal as the designers rely on post HLS synthesis results. This dissertation's fifth and final contribution is to design a fast design space explorer that combines traditional metaheuristics-based methods and machine learning to generate an optimal set of designs that are minimum both in terms of area and latency.