RF phase locked loops (PLLs) are widely used in CMOS RF front-end systems as frequency synthesizers or clock sources to generate local oscillating signals. One of the main issues in the design of the high frequency PLLs is the high power consumption of the divider block. One power reduction strategy is to use an analog frequency divider instead of a conventional digital divider. Among analog dividers, injection-locked frequency dividers (ILFDs) are attractive in frequency synthesizers because of their lower power consumptions compared to conventional digital dividers. The narrow locked regions of ILFDs has become a key issue for designers of ILFDs who need to know a priori the range of frequencies (locking range) over which they will operate. This has motivated extensive work in the literature towards modeling and predicting the behavior of these circuits in order to maximize their locking range. A variety of ILFD architectures with different locking ranges, operating frequencies and power consumptions has been implemented in the literature. However, there is still a lack of a comprehensive qualitative analysis and a corresponding robust design methodology for ILFD circuits in order to determine the locking range and the center frequency of the locked regions with respect to the ILFD{u2019}s design parameters for both small and large amplitudes of input injected signals. Current theories uses linear approximations that limit their accuracy and are suitable for small amplitudes of injected input signal. Therefore, as the first aim of this thesis, we consider this problem and analyze an ILFD circuit using nonlinear dynamical systems theory to extract a qualitative analysis as well as a design methodology that can be attractive for people from both the academic and industrial communities. Generally, injection-locked frequency divider circuits can be classified into two major families: Ring Oscillator based ILFDs and LC Oscillator based ILFDs. A circuit designer always has trade-offs in selecting an architecture from these two categories. The trade-offs are: for a given power budget, Ring Oscillator based ILFDs are compact and have wider locked regions but are noisy, whereas LC oscillators consume considerably more chip area and have narrower locked regions but have lower inherent noise. In this thesis, we consider a complementary differential LC ILFD which is a specific LC ILFD architecture that has excellent noise performance.