This thesis presents the design of a new CMOS Voltage Controlled Oscillator and a frequency divider, both of which form important blocks in the design of a PLL synthesizer. These components are important because they operate at the highest frequencies within the PLL and also consume most of the power as compared to the other components. Both these circuits have been an active topic of research in recent years especially with the scaling of technology bringing hopes of complete system-on-chip (SOC) integration at RF frequencies. The circuits in this thesis are designed for 5 GHz applications, mainly for the IEEE Wireless Local Area Network (WLAN) 802.11a standard which spans the frequency range from 5.14 GHz to 5.72 GHz. The first part of the thesis is an introduction to receiver architectures, VCO's and frequency dividers in general. The second part deals with the design, analysis and simulation results of a novel VCO presented in this work. The VCO achieves a tuning range of 130 MHz around a center frequency of 5.70 GHz and a low phase noise of -114 dBc/Hz at an offset of 1 MHz. The third part presents the design approach adopted here to designing a high frequency divider using dynamic logic and its simulation results. The logic used here is True Single Phase Clocking (TSPC), which makes use of a single clock thereby avoiding the problems of clock skew and loading. Two main blocks have been presented, the divide-by-2 and divide-by-2/3. These blocks are then cascaded to achieve higher division ratios.