A Comparative Study of Low Phase Noise Voltage-controlled Oscillators (VCOs) in CMOS Technology

A Comparative Study of Low Phase Noise Voltage-controlled Oscillators (VCOs) in CMOS Technology
Author: Hu Jing Yao
Publisher:
Total Pages: 0
Release: 2006
Genre:
ISBN:

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Voltage controlled oscillators (VCOs) are key components in frequency synthesizers for Radio Frequency (RF) wireless communications. The design of monolithic VCOs with standard CMOS processes has been the object of several recent research projects. The common goal of these attempts has been to investigate the possibility of meeting the very demanding VCO phase noise specifications without making use of bipolar processes or external components. Two categories of VCOs are studied in this thesis, one involving an inductor, and the other is inductor free, which is a ring oscillator. The study of the phase noise performance of complementary LC VCO shows that most of the phase noises come from the tail current. A modification has been made based on this topology, where the tail transistor is removed. However this brings another problem: higher power consumption. To overcome this problem, sub-threshold techniques have been used leading to sub-threshold LC VCO. A Ring oscillator is designed at the end because of its wide tuning range and ease of implementation. Schematic simulations, layout and post-layout simulations are accomplished using TSMC 0.18 um CMOS technology. The performances of the three types of VCOs are compared regarding the oscillating frequency, phase noise and tuning range. All of these can be used in the Bluetooth applications. In addition, the figure of merit (FOM) of the designed VCOs is compared with work by other researchers.

Design of High-Performance CMOS Voltage-Controlled Oscillators

Design of High-Performance CMOS Voltage-Controlled Oscillators
Author: Liang Dai
Publisher: Springer Science & Business Media
Total Pages: 170
Release: 2012-12-06
Genre: Technology & Engineering
ISBN: 1461511453

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Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results. The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.

Microelectronics, Electromagnetics and Telecommunications

Microelectronics, Electromagnetics and Telecommunications
Author: Ganapati Panda
Publisher: Springer
Total Pages: 802
Release: 2018-11-02
Genre: Technology & Engineering
ISBN: 9811319065

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The book discusses the latest developments and outlines future trends in the fields of microelectronics, electromagnetics and telecommunication. It contains original research works presented at the International Conference on Microelectronics, Electromagnetics and Telecommunication (ICMEET 2018), organised by GVP College of Engineering (A), Andhra Pradesh, India. The respective papers were written by scientists, research scholars and practitioners from leading universities, engineering colleges and R&D institutes from all over the world, and share the latest breakthroughs in and promising solutions to the most important issues facing today’s society.

Low Power VCO Design in CMOS

Low Power VCO Design in CMOS
Author: Marc Tiebout
Publisher: Springer Science & Business Media
Total Pages: 126
Release: 2006-01-25
Genre: Technology & Engineering
ISBN: 354029256X

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This work covers the design of CMOS fully integrated low power low phase noise voltage controlled oscillators for telecommunication or datacommuni- tion systems. The need for low power is obvious, as mobile wireless telecommunications are battery operated. As wireless telecommunication systems use oscillators in frequency synthesizers for frequency translation, the selectivity and signal to noise ratio of receivers and transmitters depend heavily on the low phase noise performance of the implemented oscillators. Datacommunication s- tems need low jitter, the time-domain equivalent of low phase noise, clocks for data detection and recovery. The power consumption is less critical. The need for multi-band and multi-mode systems pushes the high-integration of telecommunication systems. This is o?ered by sub-micron CMOS feat- ing digital ?exibility. The recent crisis in telecommunication clearly shows that mobile hand-sets became mass-market high-volume consumer products, where low-cost is of prime importance. This need for low-cost products - livens tremendously research towards CMOS alternatives for the bipolar or BiCMOS solutions in use today.

A New Architecture for Low-voltage Low-phase-noise High-frequency CMOS LC Voltage-controlled Oscillator

A New Architecture for Low-voltage Low-phase-noise High-frequency CMOS LC Voltage-controlled Oscillator
Author: Anthony Dac Lieu
Publisher:
Total Pages:
Release: 2005
Genre: Electric inductors
ISBN:

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Presented in this work is a novel design technique for a low-phase-noise high-frequency CMOS voltage-controlled oscillator. Phase noise is generated from electrical noise near DC, the oscillation frequency, and its harmonics. In CMOS technology, low-frequency flicker noise dominates the close-in phase noise of the VCO. The proposed technique minimizes the VCO phase noise by seeking to eliminate the effect of flicker noise on the phase n6se. This is accomplished by canceling out the DC component of the impulse sensitivity function (ISF) corresponding to each flicker-noise source, thus preventing the up-conversion of low-frequency noise into phase noise. The proposed circuit topology is a modified version of the complementary cross-coupled transconductance VCO, where additional feedback paths are introduced such that a designer can choose the feedback ratios, transistor sizes, and bias voltages to achieve the previously mentioned design objectives. A step-by-step design algorithm is presented along with a MATLAB script to aid in the computation of the ISFs and the phase noise of the VCO. Using this algorithm, a 5-GHz VCO was designed and fabricated in a 0.18m︡ CMOS process, and then tested for comparison with simulated results.

Low-power Low-phase-noise Voltage-controlled Oscillator Design

Low-power Low-phase-noise Voltage-controlled Oscillator Design
Author: Yue Yu
Publisher:
Total Pages: 230
Release: 2006
Genre: Oscillators, Electric
ISBN:

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Abstract: The design of voltage-controlled Oscillators nowadays is all about being capable of operating at higher clock frequencies for the purpose of higher data rate, consuming less power for the purpose of longer battery life, and having better phase noise performance for the purpose of higher quality of wireless service and more efficient use of the available frequency spectrum since most of the wireless and mobile terminals that these VCOs work in are required to be able to operate in multiple RF standards to serve new generations of standards while being backward compatible with existing ones, leading to a demand for multi-standard multi-band radio operation that deals with high frequency RF signals that undergo different modulation schemes of different standards in different channels over a wide range of frequency band. A top-down system design from the PLL to the VCO is carried out to determine the specifications for a fully integrated dual-band voltage-controlled oscillator (VCO) designed for a Zero-IF WiMAX/WLAN receiver in a O.18tm CMOS technology with 1.8V supply voltage. A VCO employing a differential cross-coupled inductance-capacitance (LC) tank architecture is proposed to cover twice the desired frequency bands for WiMAX and WLAN standards in order to avoid load pulling between VCO frequency and incoming RF frequency. The switching between two bands is implemented by using two binary-weighted capacitor arrays while switching inside each sub-band is implemented by different digital control signal combinations for the binary-weighted capacitances. A phase noise of -120.7dB/Hz at 1MHz offset frequency is demonstrated for an oscillation frequency of 4.84GHz. The average power consumption of this VCO is 8.1mW. This VCO is developed as an IP (Intellectual Property) to be used in a fully integrated CMOS multi-standard WiMAX/WLAN radio allowing seamless roaming of handheld mobile devices between hotspots in future Wireless Metropolitan Area Network (WMAN). To compare the performance of ring oscillators to that of LC tank oscillators, the designs of two three-stage multiple-pass voltage-controlled ring oscillators with dual-delay paths are demonstrated where the differential delay cell utilizes both the primary loop delay and the negative skewed delay to increase the frequency of oscillation substantially and retain or even increase tuning range. Their phase noise performance is also improved by switching in and out the transistors periodically. In design I, the covered frequency range is from 0.74 GHz to 1.96 GHz, which translates to a tuning range of 90 % A phase noise of -104.995dBc/Hz is demonstrated for an oscillation frequency of 1.8535 GHz. Each stage draws a current of 4.963mA on average from a 1.8V power supply, resulting in a power consumption of 26.8mW. In design II, the covered frequency range is from 1.0478 GHz to 2.0022 GHz, which translates to a tuning range of 63%. The frequency-voltage curve is almost a perfect linear curve for V between OV and 0.9V. A phase noise of -110.O45dBc/Hz is demonstrated for an oscillation frequency of 2.00216 GHz. Each stage draws a current of 10.179mA on average from a 1.8V power supply, resulting in a power consumption of 55mW.

Wireless CMOS Frequency Synthesizer Design

Wireless CMOS Frequency Synthesizer Design
Author: J. Craninckx
Publisher: Springer Science & Business Media
Total Pages: 265
Release: 2013-06-29
Genre: Technology & Engineering
ISBN: 1475728700

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The recent boom in the mobile telecommunication market has trapped the interest of almost all electronic and communication companies worldwide. New applications arise every day, more and more countries are covered by digital cellular systems and the competition between the several providers has caused prices to drop rapidly. The creation of this essentially new market would not have been possible without the ap pearance of smalI, low-power, high-performant and certainly low-cost mobile termi nals. The evolution in microelectronics has played a dominant role in this by creating digital signal processing (DSP) chips with more and more computing power and com bining the discrete components of the RF front-end on a few ICs. This work is situated in this last area, i. e. the study of the full integration of the RF transceiver on a single die. Furthermore, in order to be compatible with the digital processing technology, a standard CMOS process without tuning, trimming or post-processing steps must be used. This should flatten the road towards the ultimate goal: the single chip mobile phone. The local oscillator (LO) frequency synthesizer poses some major problems for integration and is the subject of this work. The first, and also the largest, part of this text discusses the design of the Voltage Controlled Oscillator (VCO). The general phase noise theory of LC-oscillators is pre sented, and the concept of effective resistance and capacitance is introduced to char acterize and compare the performance of different LC-tanks.

Proceedings of the International Conference on Recent Cognizance in Wireless Communication & Image Processing

Proceedings of the International Conference on Recent Cognizance in Wireless Communication & Image Processing
Author: Nitin Afzalpulkar
Publisher: Springer
Total Pages: 964
Release: 2016-04-28
Genre: Technology & Engineering
ISBN: 8132226380

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This volume comprises the proceedings of the International Conference on Recent Cognizance in Wireless Communication & Image Processing. It brings together content from academicians, researchers, and industry experts in areas of Wireless Communication and Image Processing. The volume provides a snapshot of current progress in computational creativity and a glimpse of future possibilities. The proceedings include two kinds of paper submissions: (i) regular papers addressing foundation issues, describing original research on creative systems development and modeling; and (ii) position papers describing work-in-progress or research directions for computational creativity. This work will be useful to professionals and researchers working in the core areas of wireless communications and image processing.

Time-encoding VCO-ADCs for Integrated Systems-on-Chip

Time-encoding VCO-ADCs for Integrated Systems-on-Chip
Author: Georges Gielen
Publisher: Springer Nature
Total Pages: 118
Release: 2022-03-01
Genre: Technology & Engineering
ISBN: 3030880672

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This book demonstrates why highly-digital CMOS time-encoding analog-to-digital converters incorporating voltage-controlled oscillators (VCOs) and time-to-digital converters (TDCs) are a good alternative to traditional switched-capacitor S-D modulators for power-efficient sensor, biomedical and communications applications. The authors describe the theoretical foundations and design methodology of such time-based ADCs from the basics to the latest developments. While most analog designers might notice some resemblance to PLL design, the book clearly highlights the differences to standard PLL circuit design and illustrates the design methodology with practical circuit design examples. Describes in detail the design methodology for CMOS time-encoding analog-to-digital converters that can be integrated along with digital logic in a nanometer System on Chip; Assists analog designers with the necessary change in design paradigm, highlighting differences between designing time-based ADCs and traditional analog circuits like switched-capacitor converters and PLLs; Uses a highly-visual, tutorial approach to the topic, including many practical examples of techniques introduced.