Today’s integrated circuits (IC) are more complicated than ever before, leading to extreme long development times. Therefore, many companies have began to rely on high-level synthesis (HLS) to increase their design productivity. One of the advantages of HLS is that many Register Transfer Level (RTL) designs with different area, latency, power trade-offs can be generated within a short period of time by simply modifying the synthesis options. There is no need to re-write the code as at the RT-level using low-level Hardware Description Languages (HDLs). This process can be even automated through HLS design space exploration (DSE). HLS DSE is the automatic process of generating unique micro-architectures from an untimed behavioral description for HLS. Out of all the micro-architectures the designer is only interested in the Pareto-optimal ones. Because the search space grows exponentially with the number of synthesis options, much work in the are of HLS DSE has been done in the past. In parallel, the IC industry has moved to a fabless model due to economic reason. This leads to many security risks. Moreover, power and temperature have become major concerns in modern IC design. Much work has addressed these topics at the RT-level. However, raising the level of abstraction to the behavioral level requires us to re-think these problems as this new level of abstraction poses new challenges and opportunities to address them. In this work, we leverage the advantages of HLS for hardware security, low-power and thermal-aware design. In particular the ability to automatically generate micro-architectures with unique characteristics. In particular, we present a thermal fingerprinting and watermarking technique to protect behavioral Intellectual Properties (BIPs). We introduce an obfuscation method that partitions BIPs into Application Specific IC (ASIC) and Field Programmable Gate Arrays (FPGA) to prevent designs from being reverse engineered. We also propose a runtime micro-architectural adaptation framework for FPGAs and thermal-aware C-based VLSI design method, exploiting the ability of HLS to generate a large number of RTL designs with different power and performance trade-offs. In summary, this dissertation addresses challenges that appear when raising the level of abstraction and leverages some of the unique advantages of HLS to address them.