Synchronization plays an important and fundamental role as the timing basis in digital, analog, and RF integrated circuits (ICs), where Phase-Locked Loops (PLLs) find their versatile applications. The noise sources in a traditional PLL are mainly divided into two groups: noise before the low-pass loop filter such as the noise in the reference signal, Frequency Divider (FD), Phase Frequency Detector/Charge Pump (PFD/CP); and noise after the filter such as the Voltage Controlled Oscillator (VCO) noise and the loop filter noise. The output phase noise of the PLL is the combined contribution from these two equally important in-band and out-band noise sources. This research studies the effect of the synchronization in the PLL on the decoupling of the 3dB bandwidths for different noise sources to achieve an optimum phase noise and improved locking behavior with an attenuated reference signal injection (RI) into a ring-type delay-line Voltage Controlled Synchronous Oscillator (VCSO). This dissertation begins with the development of a generalized phase model for both LC-type and ring-type VCSOs. Next, the relationship between the device baseband noise (flicker and thermal noise) and a ring-type oscillator's phase noise is derived. In addition, noise shaping functions are introduced to describe signal injection into the VCSO to achieve suppression of the oscillator in-band phase noise. Then, the transient and steady-state behavior of a Charge-Pump PLL-RI are explained with nonlinear differential equations and the phase-plane method. The nonlinear phase equation is linearized for the small-signal condition and the s-domain noise transfer functions as well as noise bandwidths are derived for different noise sources in the major components of the PLL-RI. The effect of the loop parameters and the injection strength on the output phase noise, loop settling time, and lock in range is analyzed. The analysis is verified by the SPICE simulation and experimental results from a Charge-Pump PLL-RI using a 1GHz VCSO in GlobalFoundries 130nm standard CMOS technology. The designed VCSO occupies a core area of 0.005 mm$^2$, and operates from 0.5GHz to 1.7GHz. The PLL-RI, for first-harmonic locking applications, has a core area of 0.02 mm$^2$ and consumes 2.6mW power. When a 30dB attenuation is applied, phase noise at 1MHz and 10MHz offset are reduced from -118.8dBc/Hz (PLL) to -121.9dBc/Hz (PLL-RI), and -102.3dBc/Hz (PLL) to -128.3dBc/Hz (PLL-RI), respectively, with an integrated RMS jitter from 10KHz to 30MHz of 1.55ps. Finally, another application of the PLL-RI as an integer-N frequency synthesizer is studied and tested. The PLL-RI based frequency synthesizer with the ring-type VCSO achieves comparable noise performance with LC type PLLs, but uses a much smaller chip area and features lower power consumption. To summarize, this dissertation has throughly evaluated an oscillator and a PLL under small signal injection. Compared with the traditional PLL, the all-CMOS PLL-RI offers faster settling time, wider lock in range, and ability to decouple 3dB bandwidths for different noise sources to achieve an optimum noise performance. The applications of PLL-RIs can be extended to analog, digital, and RF systems for different timing schemes.